The popularity of computing systems continues to grow and the demand for improved processing architectures thus likewise continues to grow. Ever-increasing desires for improved computing performance/efficiency has led to various improved processor architectures. For example, multi-core processors are becoming more prevalent in the computing industry and are being used in various computing devices, such as servers, personal computers (PCs), laptop computers, personal digital assistants (PDAs), wireless telephones, and so on.
In the past, processors such as central processing units (CPUs) featured a single execution unit to process instructions of a program. More recently, computer systems are being developed with multiple processors in an attempt to improve the computing performance of the system. In some instances, multiple independent processors may be implemented in a system. In other instances, a multi-core architecture may be employed, in which multiple processor cores are amassed on a single integrated silicon die. Each of the multiple processors (e.g., processor cores) can simultaneously execute program instructions. This parallel operation of the multiple processors can improve performance of a variety of applications.
Various devices are known that are reconfigurable. Examples of such reconfigurable devices include field-programmable gate arrays (FPGAs). A field-programmable gate array (FPGA) is a well-known type of semiconductor device containing programmable logic components called “logic blocks”, and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memories. A hierarchy of programmable interconnects allows logic blocks to be interconnected as desired by a system designer. Logic blocks and interconnects can be programmed by the customer/designer, after the FPGA is manufactured, to implement any logical function, hence the name “field-programmable.”
Configurations of the foregoing FPGAs may be utilized to provide reconfigurable processors, wherein binary files for implementing gate netlists designed to configure the FPGA for particular reconfigurable processor operation are loaded onto the FPGA, in the form of a loadable instruction set, in order to provide it with a desired operational “personality” (e.g., an instruction set optimized for providing particular operations, such as floating point calculations, graphics rendering, cryptographic functions, etc.). For example, one or more FPGA may be provided in association with a CPU (e.g., a fixed instruction set host processor, such as a processor implementing a x86 instruction set) to provide a heterogeneous co-processor configuration, whereby the FPGA may be dynamically configured to provide co-processor functionality optimized with respect to a current operation or use of the host processor. Such dynamically reconfigurable heterogeneous co-processor implementations provide advantages in functionality and performance.
However, creating the instruction sets to implement FPGA personalities for providing desired operations has historically been challenging. In particular, the hardware level implementation of the reconfigurable aspect of such FPGAs has generally required uniquely talented individuals, having skill sets and detailed knowledge of hardware configuration and software coding. Accordingly, the development of instruction sets for use with respect to reconfigurable processors has been somewhat limited and has generally required appreciable development time.